This invention relates generally to the design of electronic circuits and more particularly to the automated design of integrated circuits by means of behavioral synthesis tools.
The motivation for automation of integrated circuit design is the ever increasing complexity of integrated circuits. Since 1960 the number of gates on an integrated circuit chip has doubled approximately every two years. Currently, it is not unusual for a single integrated circuit chip to include hundreds of thousands of gates. Behavioral synthesis tools are emerging to help integrated circuit designers to deal with this complexity.
A behavioral synthesis tool typically comprises a behavioral synthesis program running on a general purpose digital computer. Ideally, the behavioral synthesis program takes a user's description of a circuit's behavior and then produces a corresponding circuit structure. By "behavior" it is meant that a user does not have to describe the structural components of a circuit but rather what the circuit does and how it operates. This user's description is written in a hardware description language (HDL) such as VERILOG (a trademark of Cadence, Inc.) or the public domain language VHDL. The VHDL hardware description language is specified by the IEEE as VHDL standard version 1076B which was released in 1987.
In FIG. 1, a prior art routine for producing integrated circuit masks from a hardware description language is shown. A behavioral synthesis program 10 typically includes a net expression routine 12 (sometimes called a level one synthesis routine) and a structure synthesis routine 14 (sometimes called a level two synthesis routine). The behavior of an integrated circuit (I.C.) is coded into a hardware description language and is received by the net expression routine 12 which produces a series of net expressions as illustrated by the single net expression in FIG. 1A. A net expression is a parse graph or tree which defines the output of a circuit solely in terms of its input signals. Examples of net expressions include: "IN1+IN2+CARRY"; "(e2)?e1:e2;" and "C." These net expressions are input into the structure synthesis routine 14 which produces gate-level descriptions of the I.C. circuitry. Behavioral synthesizers incorporating net expression routines and structure synthesis routines are commercially available from Synopsis, Inc.
The gate-level descriptions provided by a behavioral synthesis program 10 can be further processed in a chip compiler program 16 which produces device-level descriptions of the circuitry and in a mask layout program 18 which will use the device-level descriptions produced by the chip compiler to produce production-worthy integrated circuit masks. Chip compiler programs and mask layout programs are commercially available from VLSI, Inc. of San Jose, Calif.
A problem with prior art behavioral synthesis programs is that they cannot directly synthesize the circuit structure for a high impedance buffer. As a result, integrated circuit designers had to manually specify the structure, data inputs and control inputs for every high impedance buffer they wished to design into the circuit. This is illustrated in FIGS. 1 and 1B where the high impedance structures 20 and inputs D(data) and C(control) must be manually entered into the structure synthesis routine 14 by the circuit designer.
This step of manually entering the high impedance structure and inputs into the structure synthesis routine partially defeats the purpose of the behavioral synthesizer program, which is to free the integrated circuit designer from gate-level design work. Despite the disadvantages of manually specifying high impedance structures and control signals, designers of behavioral synthesis programs have not previously supported the synthesis of high impedance structures due to the complexities of handling high impedance states within the net expression routine.